The present invention relates generally to printed circuit boards (PCB), and more particularly to printed circuit boards laminated without fiber reinforced binders.
Current market trends in the electronic industry are to decrease size while increasing device speed, capability and interconnection density. A high interconnection density requires multilayer printed circuit boards having two or more layers of interconnections. Typically, there are four to eight layers, as specified, for example, by the Personal Computer Memory Card International Association (PCMCIA) manufacturing guidelines and tending to steadily rise.
Increased signal speed creates a greater need for component and circuitry impedance matching. Current technological developments require less distortion in signal propagation and a need for controlled impedance for impedance matching. High signal propagation speed requires a lower insulator dielectric constant. Reduced cross-talk requires reduced dielectric thickness, and cost and waste must be minimized.
Current state of the art multilayer printed circuit boards consist of two or more layers of patterned conductive sheets separated by an insulating material consisting of a glass fiber reinforced resin. Interconnections between different layers are provided using via holes through the insulating material plated with metal. Via holes may be through holes, blind vias or buried vias. Through holes pass through the entire thickness of the printed circuit board. Blind vias and buried vias pass through only part of the board, with the blind vias having an end exposed, and the buried vias having neither one of the ends exposed.
Multilayer PC boards are produced by laminating cores, prepreg and optionally carrier-mounted copper foil. Prepregs are sheets of glass fiber reinforced resin which is dried but not cured. This material is called "B" stage. Cores are fully cured ("C" stage) fiber reinforced resin (core material) covered with copper foil, usually on both sides. "A" stage is the resin compound in a liquid form with its solvent carrier.
After patterning the copper on the "inner layers" and subjecting them to an oxide process as known in the art, the cores are stacked with prepreg inserted between them. The outermost components of the stack are cores (core cap) or carrier-mounted copper foil (foil cap). The stack is laminated using heat and pressure such that the resin in the prepreg is fully cured. Plated via holes may be provided for interlayer contact by mechanically, laser or plasma drilling through the laminated structure followed by copper plating. Blind vias may be provided by laser or plasma drilling partly through the structure followed by plating, or by laminating a subassembly, providing through-holes and then laminating an additional layer on one side followed by plating. Buried vias may be provided by producing a blind via and laminating additional layers on the exposed end of the hole or by providing a through hole and laminating additional layers on both sides. Between drilling and the additional laminating, the following steps are carried out. The through holes are electroless plated with copper, the exposed copper is patterned, and then additional copper is electroplated onto the traces.
Blind vias may be provided by laser/plasma drilling because the hole stops when reaching a copper layer. The laser/plasma drilling is uneven if the material is inhomogeneous. Blind vias cannot be produced directly by mechanical drilling.
Heat sinks may be attached to printed circuit boards by using an adhesive sheet with openings cut in the areas where components will be assembled.
Conventional PCB fabrication methods require 8 to 28 mils (thousandths of an inch) core material thickness to build 4 to 10 layers into a circuit board; 5 mil core material is employed for applications requiring more than 10 layers. Standard glass reinforced prepreg has a dielectric constant of 4.3-4.6 at 1 MHz and a glass transition temperature (Tg) of approximately 130C. Prepreg has a dielectric constant of 4.2 to 4.8 due to the combination of fiberglass dielectric constant of 6.3 and resin dielectric constant of 3.8. As discussed above, a reduced dielectric constant leads to an increased signal propagation velocity. For example, a 19% reduction in the dielectric constant results in a 11% rise of the signal propagation velocity.
To achieve a greater layer count in a multilayer board, the thickness of the prepreg material must be decreased to less than 5 mils. The minimum processing thickness of prepreg in production volumes is 3 to 5 mils. Thinner prepreg is more likely to provide insufficient resin during lamination. Processing material with a core thickness of less than 5 mils exceeds most current process and equipment designs and capabilities.
PCMCIA manufacturing guidelines specify a finished thickness of 30 mil maximum. Current conventional processes require 2 to 3 mil core material to achieve 6 to 8 layers with a thickness of less than 30 mil. Processing core material of less than 5 mil exceeds standard process capabilities in handling and transfer systems for conveyor driven processes. Upgrading to accommodate thinner material processing requires high capital investments.
Thinner PCB's require a single ply of prepreg (single fiberglass weave) for bonding inner layers. Suitable prepreg exceeds 2 mils thickness in a single ply and has a loose fiber weave. The result is overall mechanical weakness, poor dimensional stability and resin starvation.
Current restraints of laser and plasma drilling technology are the dissimilar resin and fiberglass properties (i.e. melting points). The complex process of material removal (vaporization) is uneven due to the dissimilar melting points.
A major factor inhibiting fine line technology is surface smoothness. Smoother surfaces permit straighter traces. On a flat surface, a higher trace resolution is achieved. Weave texture protrusion through Cu foil limits the achievement of finer traces.
Currently, patterned adhesive sheets are needed for heat sink attachment.
A recently developed technique for PCB fabrication is the Surface Laminar Circuit (SLC) technique. This technique produces a surface laminar layer built up on a copper-clad glass fiber reinforced epoxy sheet. The surface laminar layer is made of photosensitive epoxy dielectric layers and plated copper wiring layers. Interconnections between the wiring layers are provided by photo processed via holes made in the dielectric layer.